Integrated circuit (IC) process limitations associated with decreasing minimum feature size tend to favor multiple photoresist mask patterns to achieve a specified minimum feature size with available optical photoresist mask patterning equipment. For example, double patterning, using two mask layers, and triple patterning, using three mask layers, have been used to fabricate semiconductor devices. However, decomposition of a single photoresist mask pattern into three separate mask patterns is currently a labor-intensive, trial and error process. Furthermore, whether or not a photoresist mask pattern will ultimately be capable of being decomposed into three photoresist mask patterns with present methodologies is often not known before significant decomposition efforts have already been employed, resulting in wasted effort.